1. Field of the Invention
This invention relates to a method of isolating semiconductor devices constructed on a common substrate. The invention is particularly useful in Bi-CMOS applications in which bipolar semiconductor devices must be isolated from each other and from CMOS devices.
2. Description of Related Art
Bi-CMOS technology permits bipolar and CMOS transistors to be constructed on a common semiconductor substrate. The combination of these two types of devices provides higher performance than CMOS devices alone, without the higher power consumption that would be required for a device constructed entirely from bipolar transistors.
One of the difficulties encountered in implementing bi-CMOS technology is isolating the bipolar devices from other devices on the common substrate. Shallow trench isolation (STI), which may be used for isolation of the CMOS elements, does not provide sufficient isolation for minimum size bipolar devices.
Bipolar devices constructed over a buried sub-collector can be partially isolated with the same STI regions used to isolate the CMOS elements. However, the isolation provided by the STI region is insufficient to prevent current leakage under the STI region. This current leakage seriously degrades device performance. Several approaches have been employed to eliminate the leakage path.
One solution is to use deep trench isolation, deeper than a typical STI region and sufficiently deep that the isolation region extends from the surface to the buried sub-collector. Another approach is to use a thin epitaxial layer such that the depth of the STI isolation region is sufficient to contact the buried sub-collector.
Another solution to the leakage problem is to form a second lightly doped n-type region by ion implantation to the structure above the subcollector. Yet another approach which has been tried, is the use of an additional mask to form an n+ isolation ring under the STI isolation region. All of these approaches, while partially successful, add process complexity, decrease device performance or increase device size.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method of isolating semiconductor devices that minimizes additional process complexity and avoids increasing device size.
It is another object of the present invention to provide a method of isolating semiconductor devices wherein the isolation region is automatically aligned relative to the semiconductor device to be isolated by that region.
A further object of the invention is to provide a method of forming the isolation region using dual-tone resist which has the capability of defining three separate regions with a single mask.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.